1. Field of the Invention
The present invention generally relates to level shift circuits, and particularly relates to a level shift circuit that receives a pair of input signals having two complementary levels with signal amplitudes ranging between a first predetermined positive-side power supply voltage and a predetermined negative-side power supply voltage, and produces a pair of output signals having two complementary levels by level-shifting the received signals to signals having amplitudes ranging between a second predetermined positive-side power supply voltage larger than the first predetermined positive-side power supply voltage and the predetermined negative-side power supply voltage
2. Description of the Related Art
FIG. 6 is a circuit diagram showing an example of the configuration of a level shift apparatus including a related-art level shift circuit.
The level shift apparatus 101 shown in FIG. 6 receives a signal output from an internal circuit 102 that operates by use of a first predetermined positive-side power supply voltage VDD1 (e.g., 1.2 V) as a power supply. The level shift apparatus 101 generates a pair of signals by level-shifting the received signal and a signal having a signal level inverse to the signal level of the received signal for provision to an external circuit 103 that operates by use of a second positive-side power supply voltage VDD2 (e.g., 3.3 V) as a power supply. As shown in FIG. 6, the level shift apparatus 101 includes an inverter circuit 104 operating by use of the first positive-side power supply voltage VDD1 as a power supply as does the internal circuit 102, and also includes a level shift circuit 105 operating by use of the second positive-side power supply voltage VDD2 as a power supply as does the external circuit 103. The level shift circuit 105 includes a level shift circuit unit 106 and a waveform shaping circuit unit 107. The level shift circuit unit 106 receives a signal INA output from the internal circuit 102, and also receives a signal INB having a signal level inverse to the signal level of the signal INA. The level shift circuit unit 106 shifts the levels of the received signals INA and INB to produce signals OUTA1 and OUTB1. The waveform shaping circuit unit 107 shapes the waveforms of the signals OUTA1 and OUTB1 output from the level shift circuit unit 106, thereby outputting signals OUTA and OUTB to the external circuit 103.
In FIG. 6, as the signal INA having a LOW level is supplied from the internal circuit 102, the signal INB output from the inverter circuit 104 becomes a HIGH level. As the LOW-level signal INA and the HIGH-level signal INB are supplied to the level shift circuit unit 106, a P-channel-type MOS transistor (hereinafter referred to as “PMOS transistor”) P104 and N-channel-type MOS transistor (hereinafter referred to as “NMOS transistor”) N103 are turned off, and a NMOS transistor N102 and PMOS transistor P105 are turned on. In response to the turning-on of the NMOS transistor N102, a PMOS transistor P103 is turned on, so that the output signal OUTA and output signal OUTB are set to LOW level and HIGH level, respectively.
When the signal INA changes from the LOW level to the HIGH level, the signal INB output from the inverter circuit 104 changes from the HIGH level to the LOW level. As the HIGH-level signal INA and the LOW-level signal INB are supplied to the level shift circuit unit 106, the NMOS transistor N102 and the PMOS transistor P105 are turned off, and the NMOS transistor N103 and PMOS transistor P104 are turned on. In response to the turning-on of the NMOS transistor N103, a joint point between the PMOS transistor P105 and the NMOS transistor N103 is set to a LOW voltage level, so that the output signal OUTB1 is changed to the LOW level, and, also, the PMOS transistor P102 is turned on. As the PMOS transistor 102 is turned on, a joint point between the PMOS transistor P104 and the NMOS transistor N102 is set to a HIGH voltage level since the PMOS transistor P104 is already in the turned-on state. This results in the output signal OUTA1 being set to the HIGH level.
As the signal INA changes from the HIGH level to the LOW level, the signal INB output from the inverter circuit 104 changes from the LOW level to the HIGH level. As the LOW-level signal INA and the HIGH-level signal INB are supplied to the level shift circuit unit 106, the PMOS transistor P104 and NMOS transistor N103 are turned off, and the NMOS transistor N102 and PMOS transistor P105 are turned on. In response to the turning-on of the NMOS transistor N102, a joint point between the PMOS transistor P104 and the NMOS transistor N102 is set to a LOW voltage level, so that the output signal OUTA is changed to the LOW level, and, also, the PMOS transistor P103 is turned on. As the PMOS transistor 103 is turned on, a joint point between the PMOS transistor P105 and the NMOS transistor N103 is set to a HIGH voltage level since the PMOS transistor P103 is already in the turned-on state. This results in the output signal OUTB being set to the HIGH level.
There are also related-art level shift apparatuses in which the level shift circuit has a second level shift circuit unit added thereto, which operates by use of a third positive-side power supply voltage VDD3 as a power supply higher than the first positive-side power supply voltage VDD1 and lower than the second positive-side power supply voltage VDD2 (see Patent Document 1, for example) FIG. 7 is a circuit diagram showing an example of the configuration of such related-art level shift circuit. As shown in FIG. 7, a second level shift circuit unit 202 provided in the level shift circuit 105 has the same configuration as the level shift circuit unit 106. In this level shift apparatus 201, the second level shift circuit unit 202 receives signals having an amplitude Am1 ranging between the first positive-side power supply voltage VDD1 and a negative-side power supply voltage as they are supplied from the internal circuit (not shown) and the inverter circuit 104. The second level shift circuit unit 202 converts these received signals into signals having an amplitude Am2 ranging between the third positive-side power supply voltage VDD3 and the negative-side power supply voltage where the third positive-side power supply voltage VDD3 is lower than the second positive-side power supply voltage VDD2. After this, the level shift circuit unit 106 converts the signals having the amplitude Am2 into signal having an amplitude Am3 ranging between the second positive-side power supply voltage VDD2 and the negative-side power supply voltage for provision to the external circuit (not shown).
Further, related-art level shift circuits used in level shift apparatuses include a type as shown in FIG. 8 (see Patent Document 2, for example) In this type, input nodes IN1 and IN2 receive the input signals INA and INB, respectively, which have amplitude ranging between the first positive-side power supply voltage VDD1 and the negative-side power supply voltage, and output nodes OUT1 and OUT2 output the output signals OUTA and OUTB, respectively, which have amplitude ranging between the second positive-side power supply voltage VDD2 and the negative-side power supply voltage. A level shift circuit unit is provided with these nodes IN1, IN2, OUT1, and OUT2, and includes NMOS transistors N301 and N302 and PMOS transistors P305 and P306. A current mirror circuit unit is provided to charge the output nodes OUT1 and OUT2, and includes PMOS transistors P301 through P304. Further, a switch circuit unit is provided to drive the current mirror circuit unit during an interval from the reversal of the input signals INA and INB to the reversal of the output signals OUTA and OUTB, and includes NMOS transistors N303 through N306.
[Patent Document 1] Japanese Patent Application Publication No. 9-148913
[Patent Document 2] Japanese Patent Application Publication No. 2002-76882
FIG. 9 is a timing chart showing an example of the operation of the level shift apparatus 101 shown in FIG. 6. The level shift circuit unit 106 produces the signals OUTA and OUTB having the HIGH level if the received signals OUTA1 and OUTB1 have voltages larger than a predetermined threshold, and produces the signals OUTA and OUTB having the LOW level if the received signals OUTA1 and OUTB1 have voltages lower than or equal to the predetermined threshold.
As shown in FIG. 9, the input signal INA input from the internal circuit 102 into the level shift circuit 105 and the input signal INB input from the inverter circuit 104 into the level shift circuit 105 are complementary signals that have signal levels complementary to each other. The duty cycle of the input signals INA and INB is 50%. The output signals OUTA1 and OUTB1 output from the level shift circuit unit 106, however, are provided such that one of the output signals changes to the HIGH level after the other changes to the LOW level, resulting in the former having a slow signal rise. Consequently, the signals OUTA and OUTB made by shaping the waveform of the output signals OUTA1 and OUTB1 are not provided as complementary signals, having different duty cycles and phases than the input signals INA and INB. Accordingly, the related-art level shift circuit has a problem (first problem) in that the duty cycle and phase differ between the input signals INA and INB and the output signals OUTA and OUTB.
Further, if a difference between the power supply voltages VDD1 and VDD2 is large as in the case of 1.2 V and 3.3 V in FIG. 6, in order for the level shift circuit 105 to operate properly, the on-resistance of each of the NMOS transistors N102 and N103 provided in the level shift circuit unit 106 must be smaller than a sum of the on-resistances of the PMOS transistors that are connected in series to each of the NMOS transistors N102 and N103. If the NMOS transistor N102, PMOS transistor P104, and PMOS transistor P102 have on-resistances Rn1, Rp1, and Rp2, respectively, the condition Rn1<Rp1+Rp2 must be satisfied. In order to satisfy this condition, each of the NMOS transistors N102 and N103 needs to be so designed as to have an extremely large device size, or each of the PMOS transistors P102 through P105 needs to be so designed as to have an extremely small device size. The former design strategy results in the size of the level shift circuit 105 being extremely large, and the latter design strategy results in the speed of voltage-level conversion by the level shift circuit 105 being extremely slow. This is a second problem of the related-art level shift circuit.
As shown in FIG. 7, the level shift circuit 105 of the level shift apparatus 201 may be provided with the second level shift circuit unit 202 that operates by use of the power supply voltage VDD3 as a power supply. This provision makes it possible to reduce a voltage difference between the input signals and the output signals for each of the level shift circuit units 106 and 202. As a result, it is possible to allow the level shift circuit 105 to operate properly without changing the device size of each of the transistors provided in the level shift circuit 105. The use of such a level shift circuit 105, however, necessitates the new power supply voltage VDD3. Also, the two output signals of each of the level shift circuit units 106 and 202 are provided such that one of the output signals changes to the HIGH level after the other changes to the LOW level, resulting in a slow signal rise. This creates a difference between the rise time and fall time of the output signals, so that both the duty cycle and the phase differ between the input signals into the level shift circuit 105 and the output signals from the level shift circuit 105. In order to obviate this, the speed of signal-level conversion at each of the level shift circuit units 106 and 202 needs to be increased. Namely, a ratio of the device size of the PMOS transistors to the device size of the NMOS transistors in each of the level shift circuit units 106 and 202 needs to be increased. Thus, the second problem cannot be overcome after all. In other words, it is impossible to obviate the first problem and the second problem simultaneously with respect to the level shift circuit 105.
The level shift circuit 105 shown in FIG. 8 can overcome the second problem whilst it is a single circuit. Even if this level shift circuit 105 is used, however, one of the output signals OUTA1 and OUTB1 changes to the HIGH level after the other changes to the LOW level. As a result, the output signal OUTA1 and OUTA2 and the signals obtained by shaping the waveforms of these signals are not complementary signals, having different duty cycles and phases that the inputs signals INA and INB. Namely, the use of the level shift circuit 105 shown in FIG. 8 cannot obviate the first problem and the second problem at the same time.
Accordingly, there is a need for a level shift circuit that can properly operate even when a voltage difference between input signals and output signals is large, and that can maintain the same duty cycle and phase between the input signals and the output signals.